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| MCP6291/1R/2/3/4/5 1.0 mA, 10 MHz Rail-to-Rail Op Amp Features * * * * * * * * Gain Bandwidth Product: 10 MHz (typical) Supply Current: IQ = 1.0 mA Supply Voltage: 2.4V to 6.0V Rail-to-Rail Input/Output Extended Temperature Range: -40C to +125C Available in Single, Dual and Quad Packages Single with CS (MCP6293) Dual with CS (MCP6295) Description The Microchip Technology Inc. MCP6291/1R/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a 10 MHz Gain Bandwidth Product (GBWP) and a 65 phase margin. This family also operates from a single supply voltage as low as 2.4V, while drawing 1 mA (typical) quiescent current. In addition, the MCP6291/1R/2/3/4/5 supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS - 300 mV. This family of operational amplifiers is designed with Microchip's advanced CMOS process. The MCP6295 has a Chip Select (CS) input for dual op amps in an 8-pin package. This device is manufactured by cascading the two op amps, with the output of op amp A being connected to the non-inverting input of op amp B. The CS input puts the device in a Low-power mode. The MCP6291/1R/2/3/4/5 family operates over the Extended Temperature Range of -40C to +125C. It also has a power supply range of 2.4V to 6.0V. Applications * * * * * * Automotive Portable Equipment Photodiode Amplifier Analog Filters Notebooks and PDAs Battery-Powered Systems Design Aids * * * * * * SPICE Macro Models FilterLab(R) Software MindiTM Simulation Tool MAPS (Microchip Advanced Part Selector) Analog Demonstration and Evaluation Boards Application Notes Package Types MCP6291 PDIP, SOIC, MSOP NC 1 VIN _ MCP6291 SOT-23-5 VOUT 1 VSS 2 VIN+ 3 4 VIN- + 5 VDD MCP6291R SOT-23-5 VOUT 1 VIN+ 3 + VDD 2 5 VSS 4 VIN- MCP6292 PDIP, SOIC, MSOP VOUTA 1 VINA 2 VINA+ 3 VSS 4 _ 8 NC + 7 VDD 6 VOUT 5 NC 8 VDD -+ +7 VOUTB 6 VINB_ 5 VINB+ 2 VIN+ 3 VSS 4 MCP6293 PDIP, SOIC, MSOP NC 1 VIN_ 2 VIN+ 3 VSS 4 + 8 CS 7 VDD 6 VOUT 5 NC VOUT 1 VSS 2 VIN+ 3 MCP6293 SOT-23-6 6 VDD 5 CS 4 VIN- + MCP6294 PDIP, SOIC, TSSOP VOUTA 1 VINA_ 2 VINA+ 3 VDD 4 VINB+ 5 VINB_ 6 VOUTB 7 14 VOUTD MCP6295 PDIP, SOIC, MSOP VOUTA/VINB+ 1 VINA_ 2 VINA+ 3 VSS 4 -+ +- - + + - 13 VIND_ 12 VIND+ 11 VSS 10 VINC+ -+ +- 9 V _ INC 8 VOUTC 8 VDD 7 VOUTB _ 6 VINB 5 CS (c) 2007 Microchip Technology Inc. DS21812E-page 1 MCP6291/1R/2/3/4/5 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section 4.1.2 "Input Voltage and Current Limits". Absolute Maximum Ratings VDD - VSS ........................................................................7.0V Current at Input Pins .....................................................2 mA Analog Inputs (VIN+, VIN-) ........ VSS - 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS - 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD - VSS| Output Short Circuit Current .................................Continuous Current at Output and Supply Pins ............................30 mA Storage Temperature....................................-65C to +150C Maximum Junction Temperature (TJ) ......................... .+150C ESD Protection On All Pins (HBM; MM) .............. 4 kV; 400V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VOUT VDD/2, VCM = VDD/2, VL = VDD/2, RL = 10 k to VL and CS is tied low (refer to Figure 1-2 and Figure 1-3). Parameters Input Offset Input Offset Voltage Input Offset Voltage (Extended Temperature) Input Offset Temperature Drift Power Supply Rejection Ratio Input Bias Current At Temperature At Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode (Note 4) Common Mode Input Range Common Mode Rejection Ratio Common Mode Rejection Ratio Open-Loop Gain DC Open-Loop Gain (Large Signal) Output Maximum Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: 3: 4: 5: VDD IQ 2.4 0.7 -- 1.0 6.0 1.3 V mA TA = -40C to +125C (Note 5) IO = 0 VOL, VOH ISC VSS + 15 -- -- 25 VDD - 15 -- mV mA 0.5V Input Overdrive AOL 90 110 -- dB VOUT = 0.2V to VDD - 0.2V, VCM = VSS (Note 1) VCMR CMRR CMRR VSS - 0.3 70 65 -- 85 80 VDD + 0.3 -- -- V dB dB VCM = -0.3V to 2.5V, VDD = 5V VCM = -0.3V to 5.3V, VDD = 5V VOS VOS VOS/TA PSRR IB IB IB IOS ZCM ZDIFF -3.0 -5.0 -- 70 -- -- -- -- -- -- -- -- 1.7 90 1.0 50 2 1.0 1013||6 1013||3 +3.0 +5.0 -- -- -- 200 5 -- -- -- mV mV V/C dB pA pA nA pA ||pF ||pF VCM = VSS (Note 1) TA = -40C to +125C, VCM = VSS (Note 1) TA = -40C to +125C, VCM = VSS (Note 1) VCM = VSS (Note 1) Note 2 TA = +85C (Note 2) TA = +125C (Note 2) Note 3 Note 3 Note 3 Sym Min Typ Max Units Conditions Input Bias, Input Offset Current and Impedance The MCP6295's VCM for op amp B (pins VOUTA/VINB+ and VINB-) is VSS + 100 mV. The current at the MCP6295's VINB- pin is specified by IB only. This specification does not apply to the MCP6295's VOUTA/VINB+ pin. The MCP6295's VINB- pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD - 100 mV. The MCP6295's VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL. All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 2.4V and or 5.5V. DS21812E-page 2 (c) 2007 Microchip Technology Inc. MCP6291/1R/2/3/4/5 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3). Parameters AC Response Gain Bandwidth Product Phase Margin at Unity-Gain Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Eni eni ini -- -- -- 4.2 8.7 3 -- -- -- VP-P nV/Hz fA/Hz f = 0.1 Hz to 10 Hz f = 10 kHz f = 1 kHz GBWP PM SR -- -- -- 10.0 65 7 -- -- -- MHz V/s G = +1 V/V Sym Min Typ Max Units Conditions MCP6293/MCP6295 CHIP SELECT (CS) SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3). Parameters CS Low Specifications CS Logic Threshold, Low CS Input Current, Low CS High Specifications CS Logic Threshold, High CS Input Current, High GND Current per Amplifier Amplifier Output Leakage Dynamic Specifications (Note 1) CS Low to Valid Amplifier Output, Turn-on Time CS High to Amplifier Output High-Z Hysteresis Note 1: tON -- 4 10 s CS Low 0.2 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.9 VDD/2, VDD = 5.0V CS High 0.8 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.1 VDD/2 VDD = 5V VIH ICSH ISS -- 0.8 VDD -- -- -- -- 0.7 -0.7 0.01 VDD 2 -- -- V A A A CS = VDD CS = VDD CS = VDD VIL ICSL VSS -- -- 0.01 0.2 VDD -- V A CS = VSS Sym Min Typ Max Units Conditions tOFF VHYST -- -- 0.01 0.6 -- -- s V The input condition (VIN) specified applies to both op amp A and B of the MCP6295. The dynamic specification is tested at the output of op amp B (VOUTB). (c) 2007 Microchip Technology Inc. DS21812E-page 3 MCP6291/1R/2/3/4/5 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +2.4V to +5.5V and VSS = GND. Parameters Temperature Ranges Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT-23 Thermal Resistance, 6L-SOT-23 Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Note: JA JA JA JA JA JA JA JA -- -- -- -- -- -- -- -- 256 230 85 163 206 70 120 100 -- -- -- -- -- -- -- -- C/W C/W C/W C/W C/W C/W C/W C/W TA TA -40 -65 -- -- +125 +150 C C Note Sym Min Typ Max Units Conditions The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C. 1.1 CS VIL tON VOUT Hi-Z VIH tOFF Hi-Z VIN Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-2. The bypass capacitors are laid out according to the rules discussed in Section 4.6 "Supply Bypass". VDD RN 0.1 F 1 F VOUT CL VDD/2 RG RF VL RL ISS -0.7 A (typical) 0.7 A (typical) -1.0 mA (typical) 10 nA (typical) -0.7 A (typical) 0.7 A (typical) MCP629X ICS FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6293 and MCP6295. FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD RN 0.1 F 1 F VOUT CL VIN RG RF VL RL VDD/2 MCP629X FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. DS21812E-page 4 (c) 2007 Microchip Technology Inc. MCP6291/1R/2/3/4/5 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low. 12% 11% 10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0% 25% Percentage of Occurrences Percentage of Occurrences 840 Samples VCM = VSS 20% 15% 10% 5% 0% 840 Samples VCM = VSS TA = -40C to +125C -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 -8 -6 -4 -2 0 2 4 6 -10 8 2600 2800 Input Offset Voltage (mV) Input Offset Voltage Drift (V/C) FIGURE 2-1: 40% Input Offset Voltage. FIGURE 2-4: 30% Input Offset Voltage Drift. Percentage of Occurrences Percentage of Occurrences 35% 30% 25% 20% 15% 10% 5% 0% 210 Samples TA = 85C 25% 20% 15% 10% 5% 0% 210 Samples TA = +125C 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 0 10 20 30 40 50 60 70 80 90 100 Input Bias Current (pA) Input Bias Current (pA) FIGURE 2-2: TA = +85 C. 400 Input Bias Current at FIGURE 2-5: TA = +125 C. Input Bias Current at Input Offset Voltage (V) 350 300 250 200 150 100 50 Input Offset Voltage (V) VDD = 2.4V TA = -40C TA = +25C TA = +85C TA = +125C 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 800 VDD = 5.5V 750 700 650 600 550 500 450 400 350 300 250 200 -0.5 0.0 0.5 1.0 1.5 2.0 TA = +125C TA = +85C TA = +25C TA = -40C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.4V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. (c) 2007 Microchip Technology Inc. DS21812E-page 5 3000 10 MCP6291/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low. 700 650 600 550 500 450 400 350 300 250 200 150 100 0.0 0.5 1.0 1.5 2.0 10,000 Input Offset Voltage (V) Input Bias, Offset Currents (pA) VCM = VSS Representative Part VCM = VDD VDD = 5.5V 1,000 100 Input Bias Current Input Offset Current VDD = 5.5V VDD = 2.4V 10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 25 35 45 55 65 75 85 95 105 115 125 Output Voltage (V) Ambient Temperature (C) FIGURE 2-7: Output Voltage. 110 100 Input Offset Voltage vs. FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature. 120 110 CMRR, PSRR (dB) CMRR PSRRPSRR+ PSRR, CMRR (dB) 90 80 70 60 50 40 30 20 100 CMRR 90 80 70 60 PSRR VCM = VSS 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1 10 100 1k 10k 100k 1M -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (C) FIGURE 2-8: Frequency. 55 CMRR, PSRR vs. FIGURE 2-11: Temperature. 2.5 CMRR, PSRR vs. Ambient Input Bias, Offset Currents (pA) 35 25 15 5 -5 -15 -25 0.0 0.5 1.0 1.5 2.0 2.5 TA = +85C VDD = 5.5V Input Bias Current Input Bias, Offset Currents (nA) 45 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 TA = +125C VDD = 5.5V Input Bias Current Input Offset Current Input Offset Current 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-9: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +85C. FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +125C. DS21812E-page 6 (c) 2007 Microchip Technology Inc. MCP6291/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low. 1.6 1.4 1000 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TA = +125C TA = +85C TA = +25C TA = -40C Ouput Voltage Headroom (mV) Quiescent Current (mA/Amplifier) 100 10 VOL - VSS VDD - VOH 1 0.01 0.1 1 10 Power Supply Voltage (V) Output Current Magnitude (mA) FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. 120 100 0 -30 FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. 16 90 GBWP, VDD = 5.5V GBWP, VDD = 2.4V 85 Open-Loop Phase () 80 Phase 60 40 20 0 -20 0.1 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 -60 -90 -120 -150 -180 1 10 100 1k 10k 100k 1M -210 10M 100M 1.E+08 10 8 6 4 2 0 -50 -25 0 25 50 75 100 PM, VDD = 5.5V PM, VDD = 2.4V 75 70 65 60 55 50 125 Frequency (Hz) Ambient Temperature (C) FIGURE 2-14: Frequency. 10 Open-Loop Gain, Phase vs. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. 12 10 Falling Edge, VDD = 5.5V VDD = 2.4V Maximum Output Voltage Swing (V P-P) Slew Rate (V/s) 8 6 4 2 0 Rising Edge, VDD = 5.5V VDD = 2.4V 1 VDD = 5.5V VDD = 2.4V 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 0.1 1k 10k 100k 1M 10M -50 -25 0 25 50 75 100 125 Frequency (Hz) Ambient Temperature (C) FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-18: Temperature. Slew Rate vs. Ambient (c) 2007 Microchip Technology Inc. DS21812E-page 7 Phase Margin () Gain Gain Bandwidth Product (MHz) 14 12 Open-Loop Gain (dB) 80 MCP6291/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low. 1,000 11 Input Noise Voltage Density (nV/Hz) Input Noise Voltage Density (nV/Hz) 10 9 8 7 6 5 4 3 2 1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 f = 10 kHz VDD = 5.0V 100 10 1 0.1 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1 10 100 1k 10k 100k 1M Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-19: vs. Frequency. 35 Input Noise Voltage Density FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 10 kHz. 140 Ouptut Short Circuit Current (mA) 30 Channel-to-Channel Separation (dB) 4.0 4.5 5.0 5.5 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TA = +125C TA = +85C TA = +25C TA = -40C 130 120 110 100 1 10 100 Power Supply Voltage (V) Frequency (kHz) FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6292, MCP6294 and MCP6295 only). 1.6 1.4 1.2 Op-Amp shuts off here 1.0 Op-Amp turns on here VDD = 2.4V Op Amp shuts off Op Amp turns on VDD = 5.5V Hysteresis Quiescent Current (mA/Amplifier) Quiescent Current (mA/Amplifier) 1.2 1.0 0.8 0.6 0.4 0.2 0.0 CS swept high to low 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Hysteresis CS swept high to low CS swept low to high CS swept low to high 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) Chip Select Voltage (V) FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6293 and MCP6295 only). DS21812E-page 8 (c) 2007 Microchip Technology Inc. MCP6291/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low. 5.0 4.5 4.0 5.0 4.5 G = +1V/V VDD = 5.0V G = -1V/V VDD = 5.0V Output Voltage (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Output Voltage (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 1.E-05 Time (1 s/div) Time (1 s/div) FIGURE 2-25: Pulse Response. Large-Signal Non-inverting FIGURE 2-28: Response. Large-Signal Inverting Pulse G = +1V/V G = -1V/V Output Voltage (10 mV/div) Time (200 ns/div) Output Voltage (10 mV/div) Time (200 ns/div) FIGURE 2-26: Pulse Response. 3.0 Small-Signal Non-inverting FIGURE 2-29: Response. 6.0 Small-Signal Inverting Pulse Chip Select, Output Voltages (V) 2.5 2.0 1.5 1.0 0.5 CS Voltage Chip Select, Output Voltages (V) VDD = 2.4V G = +1V/V VIN = VSS 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 CS Voltage VDD = 5.5V G = +1V/V VIN = VSS VOUT Output On VOUT Output On Output High-Z 5.E-05 5.E-05 Output High-Z 0.0 0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05 Time (5 s/div) Time (5 s/div) FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at VDD = 5.5V (MCP6293 and MCP6295 only). (c) 2007 Microchip Technology Inc. DS21812E-page 9 MCP6291/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 k to VL, CL = 60 pF, and CS is tied low. 1.E-02 10m 1m 1.E-03 100 1.E-04 10 1.E-05 1 1.E-06 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 6 Input Current Magnitude (A) Input, Output Voltage (V) 5 4 3 2 1 0 -1 -15 -14 -13 -12 -11 -10 -9 -8 VDD = 5.0V G = +2V/V VIN VOUT +125C +85C +25C -40C -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) -7 -6 -5 Time (1 ms/div) FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-32: The MCP6291/1R/2/3/4/5 Show No Phase Reversal. DS21812E-page 10 (c) 2007 Microchip Technology Inc. MCP6291/1R/2/3/4/5 3.0 PIN DESCRIPTIONS PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6293 MCP6291R SOT-23-5 1 4 3 5 2 -- -- 1 4 3 2 5 -- -- PDIP, SOIC, MSOP 6 2 3 7 4 8 1,5 Symbol SOT-23-6 1 4 3 6 2 5 -- VOUT VIN- VIN+ VDD VSS CS NC Analog Output Inverting Input Non-inverting Input Positive Power Supply Negative Power Supply Chip Select No Internal Connection Description Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-1: MCP6291 PDIP, SOIC, MSOP 6 2 3 7 4 -- 1,5,8 TABLE 3-2: MCP6292 1 2 3 8 5 6 7 -- -- -- 4 -- -- -- -- -- PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6294 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -- -- MCP6295 -- 2 3 8 -- 6 7 -- -- -- 4 -- -- -- 1 5 Symbol VOUTA VINA- VINA+ VDD VINB+ VINB- VOUTB VOUTC VINC- VINC+ VSS VIND+ VIND- VOUTD VOUTA/VINB+ CS Analog Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Positive Power Supply Non-inverting Input (op amp B) Inverting Input (op amp B) Analog Output (op amp B) Analog Output (op amp C) Inverting Input (op amp C) Non-inverting Input (op amp C) Negative Power Supply Non-inverting Input (op amp D) Inverting Input (op amp D) Analog Output (op amp D) Analog Output (op amp A)/Non-inverting Input (op amp B) Chip Select Description 3.1 3.2 Analog Outputs Analog Inputs 3.4 Chip Select Digital Input The output pins are low-impedance voltage sources. This is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation. 3.5 Power Supply Pins The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. 3.3 MCP6295's VOUTA/VINB+ Pin The positive power supply (VDD) is 2.4V to 6.0V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors For the MCP6295 only, the output of op amp A is connected directly to the non-inverting input of op amp B; this is the VOUTA/VINB+ pin. This connection makes it possible to provide a Chip Select pin for duals in 8-pin packages. (c) 2007 Microchip Technology Inc. DS21812E-page 11 MCP6291/1R/2/3/4/5 4.0 APPLICATION INFORMATION The MCP6291/1R/2/3/4/5 family of op amps is manufactured using Microchip's state of the art CMOS process, specifically designed for low-cost, low-power and general purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6291/1R/2/3/4/5 ideal for battery-powered applications. VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. VDD D1 V1 R1 V2 R2 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) R2 > 2 mA R1 > D2 MCP629X VOUT 4.1 4.1.1 Rail-to-Rail Inputs PHASE REVERSAL The MCP6291/1R/2/3/4/5 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-32 shows the input voltage exceeding the supply voltage without any phase reversal. 4.1.2 INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. FIGURE 4-2: Inputs. Protecting the Analog It is also possible to connect the diodes to the left of the resistor R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs when the common mode voltage (VCM) is below ground (VSS); see Figure 2-31. Applications that are high impedance may need to limit the usable voltage range. VDD Bond Pad 4.1.3 VIN+ Bond Pad Input Stage Bond VIN- Pad NORMAL OPERATION VSS Bond Pad The input stage of the MCP6291/1R/2/3/4/5 op amps use two differential CMOS input stages in parallel. One operates at low common mode input voltage (VCM), while the other operates at high VCM. WIth this topology, the device operates with VCM up to 0.3V past either supply rail. The input offset voltage (VOS) is measured at VCM = VSS - 0.3V and VDD + 0.3V to ensure proper operation. The transition between the two input stages occurs when VCM = VDD - 1.1V. For the best distortion and gain linearity, with non-inverting gains, avoid this region of operation. FIGURE 4-1: Structures. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the currents and voltages at the VIN+ and VIN- pins (see Absolute Maximum Ratings " at the beginning of Section 1.0 "Electrical Characteristics"). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN-) from going too far above 4.2 Rail-to-Rail Output The output voltage range of the MCP6291/1R/2/3/4/5 op amp is VDD - 15 mV (min.) and VSS + 15 mV (maximum) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-16 for more information. DS21812E-page 12 (c) 2007 Microchip Technology Inc. MCP6291/1R/2/3/4/5 4.3 Capacitive Loads 4.4 MCP629X Chip Select Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. The MCP6293 and MCP6295 are single and dual op amps with Chip Select (CS), respectively. When CS is pulled high, the supply current drops to 0.7 A (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 M (typical) pull-down resistor connected to VSS, so it will go low if the CS pin is left floating. Figure 1-1 shows the output voltage and supply current response to a CS pulse. 4.5 Cascaded Dual Op Amps (MCP6295) - MCP629X VIN + RISO VOUT CL The MCP6295 is a dual op amp with Chip Select (CS). The Chip Select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). This is available because the output of op amp A connects to the non-inverting input of op amp B, as shown in Figure 4-5. The Chip Select input, which can be connected to a microcontroller I/O line, puts the device in Low-power mode. Refer to Section 4.4 "MCP629X Chip Select". VOUTA/VINB+ VINB- FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 100 Recommended R ISO () 1 VINA- VINA+ 2 3 A MCP6295 5 CS 6 B 7 VOUTB FIGURE 4-5: Cascaded Gain Amplifier. GN = 1 V/V GN 2 V/V 10 10 100 1,000 10,000 Normalized Load Capacitance; CL/GN (pF) The output of op amp A is loaded by the input impedance of op amp B, which is typically 1013||6 pF, as specified in the DC specification table (Refer to Section 4.3 "Capacitive Loads" for further details regarding capacitive loads). The common mode input range of these op amps is specified in the data sheet as VSS - 300 mV and VDD + 300 mV. However, since the output of op amp A is limited to VOL and VOH (20 mV from the rails with a 10 k load), the non-inverting input range of op amp B is limited to the common mode input range of VSS + 20 mV and VDD - 20 mV. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6291/1R/2/3/4/5 SPICE macro model are helpful. (c) 2007 Microchip Technology Inc. DS21812E-page 13 MCP6291/1R/2/3/4/5 4.6 Supply Bypass 4.8 PCB Surface Leakage With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high-frequency performance. It also needs a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with nearby analog parts. In applications where low input bias current is critical, Printed Circuit Board (PCB) surface-leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6291/1R/2/3/4/5 family's bias current at 25C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7. VIN- VIN+ VSS 4.7 Unused Op Amps An unused op amp in a quad package (MCP6294) should be configured as shown in Figure 4-6. These circuits prevent the output from toggling and causing crosstalk. Circuits A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. 1/4 MCP6294 (A) VDD R1 R2 VDD VREF 1/4 MCP6294 (B) VDD Guard Ring FIGURE 4-7: for Inverting Gain. 1. Example Guard Ring Layout R2 V REF = V DD -----------------R1 + R2 FIGURE 4-6: Unused Op Amps. 2. For Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. DS21812E-page 14 (c) 2007 Microchip Technology Inc. MCP6291/1R/2/3/4/5 4.9 4.9.1 Application Circuits MULTIPLE FEEDBACK LOW-PASS FILTER 4.9.3 CASCADED OP AMP APPLICATIONS The MCP6291/1R/2/3/4/5 op amp can be used in active-filter applications. Figure 4-8 shows an inverting, third-order, multiple feedback low-pass filter that can be used as an anti-aliasing filter. R1 VIN C1 R3 R2 R4 C4 VOUT C3 The MCP6295 provides the flexibility of Low-power mode for dual op amps in an 8-pin package. The MCP6295 eliminates the added cost and space in battery-powered applications by using two single op amps with Chip Select lines or a 10-pin device with one Chip Select line for both op amps. Since the two op amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps. However, there are several applications where this op amp configuration with Chip Select line becomes suitable. The circuits below show possible applications for this device. 4.9.3.1 MCP6291 VDD/2 Load Isolation FIGURE 4-8: Pass Filter. Multiple Feedback Low- With the cascaded op amp configuration, op amp B can be used to isolate the load from op amp A. In applications where op amp A is driving capacitive or low resistance loads in the feedback loop (such as an integrator circuit or filter circuit), the op amp may not have sufficient source current to drive the load. In this case, op amp B can be used as a buffer. This filter, and others, can be designed using Microchip's Filter design software. Refer to Section 5.0 "Design Aids" 4.9.2 PHOTODIODE AMPLIFIER B A MCP6295 CS VOUTB Load Figure 4-9 shows a photodiode biased in the photovoltaic mode for high precision. The resistor R converts the diode current ID to the voltage VOUT. The capacitor is used to limit the bandwidth or to stabilize the circuit against the diode's capacitance (it is not always needed). FIGURE 4-10: Buffer. Isolating the Load with a C R VOUT ID light MCP6291 VDD/2 FIGURE 4-9: Photodiode Amplifier. (c) 2007 Microchip Technology Inc. DS21812E-page 15 MCP6291/1R/2/3/4/5 4.9.3.2 Cascaded Gain 4.9.3.4 Buffered Non-inverting Integrator Figure 4-11 shows a cascaded gain circuit configuration with Chip Select. Op amps A and B are configured in a non-inverting amplifier configuration. In this configuration, it is important to note that the input offset voltage of op amp A is amplified by the gain of op amp A and B, as shown below: V OUT = V IN G A G B + V OSA G A G B + V OSB G B Where: GA GB VOSA VOSB = = = = op amp A gain op amp B gain op amp A input offset voltage op amp B input offset voltage VIN R1 RF A B VOUT Figure 4-13 shows a lossy non-inverting integrator that is buffered and has a Chip Select input. Op amp A is configured as a non-inverting integrator. In this configuration, matching the impedance at each input is recommended. R F is used to provide a feedback loop at frequencies << 1/(2R1C1) and makes this a lossy integrator (it has a finite gain at DC). Op amp B is used to isolate the load from the integrator. R2 C2 MCP6295 C1 CS Therefore, it is recommended to set most of the gain with op amp A and use op amp B with relatively small gain (e.g., a unity-gain buffer). R 1 C 1 = ( R 2 || R F )C 2 R4 R3 R2 R1 FIGURE 4-13: Buffered Non-inverting Integrator with Chip Select. 4.9.3.5 Inverting Integrator with Active Compensation and Chip Select A VIN MCP6295 B VOUT CS FIGURE 4-11: Configuration. 4.9.3.3 Cascaded Gain Circuit Figure 4-14 uses an active compensator (op amp B) to compensate for the non-ideal op amp characteristics introduced at higher frequencies. This circuit uses op amp B as a unity-gain buffer to isolate the integration capacitor C1 from op amp A and drives the capacitor with low-impedance source. Since both op amps are matched very well, they provide a high quality integrator. Difference Amplifier VIN Figure 4-12 shows op amp A as a difference amplifier with Chip Select. In this configuration, it is recommended to use well-matched resistors (e.g., 0.1%) to increase the Common Mode Rejection Ratio (CMRR). Op amp B can be used for additional gain or as a unity-gain buffer to isolate the load from the difference amplifier. R4 VIN2 R2 R1 B A MCP6295 VOUT R3 R1 C1 B A MCP6295 VOUT CS VIN1 R2 R1 FIGURE 4-14: Compensation. Integrator Circuit with Active CS FIGURE 4-12: Difference Amplifier Circuit. (c) 2007 Microchip Technology Inc. DS21812E-page 16 MCP6291/1R/2/3/4/5 4.9.3.6 Second-Order MFB Low-Pass Filter with an Extra Pole-Zero Pair 4.9.3.8 Capacitorless Second-Order Low-Pass filter with Chip Select Figure 4-15 is a second-order multiple feedback lowpass filter with Chip Select. Use the FilterLab(R) software from Microchip to determine the R and C values for the op amp A's second-order filter. Op amp B can be used to add a pole-zero pair using C3, R6 and R7. R6 C1 R3 VIN C2 R5 R4 A R2 C3 R1 R7 B VOUT The low-pass filter shown in Figure 4-17 does not require external capacitors and uses only three external resistors; the op amp's GBWP sets the corner frequency. R1 and R2 are used to set the circuit gain and R3 is used to set the Q. To avoid gain peaking in the frequency response, Q needs to be low (lower values need to be selected for R3). Note that the amplifier bandwidth varies greatly over temperature and process. However, this configuration provides a low cost solution for applications with high bandwidth requirements. MCP6295 VIN R2 R3 A R1 CS FIGURE 4-15: Second-Order Multiple Feedback Low-Pass Filter with an Extra PoleZero Pair. 4.9.3.7 Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair B VREF MCP6295 CS VOUT Figure 4-16 is a second-order, Sallen-Key low-pass filter with Chip Select. Use the FilterLab(R) software from Microchip to determine the R and C values for the op amp A's second-order filter. Op amp B can be used to add a pole-zero pair using C3, R5 and R6. R2 R1 R5 C3 R6 B FIGURE 4-17: Capacitorless Second-Order Low-Pass Filter with Chip Select. R4 VIN R3 C1 A VOUT MCP6295 C2 CS FIGURE 4-16: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. (c) 2007 Microchip Technology Inc. DS21812E-page 17 MCP6291/1R/2/3/4/5 5.0 DESIGN AIDS 5.5 Microchip provides the basic design tools needed for the MCP6291/1R/2/3/4/5 family of op amps. Analog Demonstration and Evaluation Boards 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6291/1R/2/ 3/4/5 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/analogtools. Two of our boards that are especially useful are: * P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board * P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board 5.6 Application Notes 5.2 FilterLab(R) Software Microchip's FilterLab(R) software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/ appnotes and are recommended as supplemental reference resources. ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 AN723: "Operational Amplifier AC Specifications and Applications", DS00723 AN884: "Driving Capacitive Loads With Op Amps", DS00884 AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 These application notes and others are listed in the design guide: "Signal Chain Design Guide", DS21825 5.3 MindiTM Simulator Tool Microchip's MindiTM simulator tool aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online simulation tool available from the Microchip web site at www.microchip.com/mindi. This interactive simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi simulation tool can be downloaded to a personal computer or workstation. 5.4 MAPS (Microchip Advanced Part Selector) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts. DS21812E-page 18 (c) 2007 Microchip Technology Inc. MCP6291/1R/2/3/4/5 6.0 6.1 PACKAGING INFORMATION Package Marking Information 5-Lead SOT-23 (MCP6291 and MCP6291R) Example: Device Code CJNN EVNN XXNN MCP6291 MCP6291R CJ25 Note: Applies to 5-Lead SOT-23 6-Lead SOT-23 (MCP6283) Example: Device Code CMNN XXNN MCP6293 Note: Applies to 6-Lead SOT-23 CM25 8-Lead MSOP XXXXXX YWWNNN Example: 6291E 436256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP6291 E/P256 0436 MCP6291 e3 E/P^^256 0743 OR 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: MCP6291 E/SN0436 256 MCP6291E e3 SN^^0743 256 OR Legend: XX...X Y YY WW NNN * Note: e3 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2007 Microchip Technology Inc. DS21812E-page 19 MCP6291/1R/2/3/4/5 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6294) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP6294-E/P 0436256 OR MCP6294 e3 E/P^^ 0743256 14-Lead SOIC (150 mil) (MCP6294) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6294ESL 0436256 OR MCP6294 E/SL^^ e3 0436256 14-Lead TSSOP (MCP6294) Example: XXXXXX YYWW NNN 6294EST 0436 256 DS21812E-page 20 (c) 2007 Microchip Technology Inc. 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DS21812E-page 23 MCP6291/1R/2/3/4/5 /HDG 3ODVWLF 'XDO ,Q/LQH 3 PLO %RG\ >3',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ N NOTE 1 E1 1 2 D 3 E A2 A A1 e b1 b L c eB 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 7RS WR 6HDWLQJ 3ODQH 0ROGHG 3DFNDJH 7KLFNQHVV %DVH WR 6HDWLQJ 3ODQH 6KRXOGHU WR 6KRXOGHU :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK 7LS WR 6HDWLQJ 3ODQH /HDG 7KLFNQHVV 8SSHU /HDG :LGWK /RZHU /HDG :LGWK 2YHUDOO 5RZ 6SDFLQJ 1 H $ $ $ ( ( ' / F E E H% 0,1 ,1&+(6 120 %6& 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWK WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS21812E-page 24 (c) 2007 Microchip Technology Inc. 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DS21812E-page 25 MCP6291/1R/2/3/4/5 /HDG 3ODVWLF 6PDOO 2XWOLQH 61 1DUURZ PP %RG\ >62,&@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS21812E-page 26 (c) 2007 Microchip Technology Inc. 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DS21812E-page 27 MCP6291/1R/2/3/4/5 /HDG 3ODVWLF 6PDOO 2XWOLQH 6/ 1DUURZ PP %RG\ >62,&@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 b 3 e h h A2 c A A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK &KDPIHU RSWLRQDO )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' K / / I F E D E 0,1 0,//,0(7(56 120 %6& %6& %6& %6& 5() 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( <0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS21812E-page 28 (c) 2007 Microchip Technology Inc. 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DS21812E-page 29 MCP6291/1R/2/3/4/5 NOTES: DS21812E-page 30 (c) 2007 Microchip Technology Inc. MCP6291/1R/2/3/4/5 APPENDIX A: REVISION HISTORY Revision E (November 2007) The following is the list of modifications: 1. Updated notes to Section 1.0 "Electrical Characteristics". Increased absolute maximum voltage range of input pins. Increased maximum operating supply voltage (VDD). Added Test Circuits. Added Figure 2-31 and Figure 2-32. Added Section 4.1.1 "Phase Reversal", Section 4.1.2 "Input Voltage and Current Limits", and Section 4.1.3 "Normal Operation". Added Section 4.7 "Unused Op Amps". Updated Section 5.0 "Design Aids". Corrected Package Markings. Updated Package Outline Drawing. 2. 3. 4. 5. 6. 7. 8. Revision D (December 2004) The following is the list of modifications: 1. 2. 3. 4. 5. Added SOT-23-5 packages for the MCP6291 and MCP6291R single op amps. Added SOT-23-6 package for the MCP6293 single op amp. Added Section 3.0 "Pin Descriptions". Corrected application circuits (Section 4.9 "Application Circuits"). Added SOT-23-5 and SOT-23-6 packages and corrected package marking information (Section 6.0 "Packaging Information"). Added Appendix A: Revision History. 6. Revision C (June 2004) * Undocumented changes. Revision B (October 2003) * Undocumented changes. Revision A (June 2003) * Original data sheet release. (c) 2007 Microchip Technology Inc. DS21812E-page 31 MCP6291/1R/2/3/4/5 NOTES: DS21812E-page 32 (c) 2007 Microchip Technology Inc. MCP6291/1R/2/3/4/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device - X /XX Package Examples: a) b) c) Extended Temperature, 8 lead SOIC package. MCP6291-E/MS: Extended Temperature, 8 lead MSOP package. MCP6291-E/P: Extended Temperature, 8 lead PDIP package. MCP6291T-E/OT: Tape and Reel, Extended Temperature, 5 lead SOT-23 package. MCP6291RT-E/OT: Tape and Reel, Extended Temperature, 5 lead SOT-23 package. Extended Temperature, 8 lead SOIC package. MCP6292-E/MS: Extended Temperature, 8 lead MSOP package. MCP6292-E/P: Extended Temperature, 8 lead PDIP package. MCP6292T-E/SN: Tape and Reel, Extended Temperature, 8 lead SOIC package. Extended Temperature, 8 lead SOIC package. MCP6293-E/MS: Extended Temperature, 8 lead MSOP package. MCP6293-E/P: Extended Temperature, 8 lead PDIP package. MCP6293T-E/CH: Tape and Reel, Extended Temperature, 6 lead SOT-23 package. MCP6294-E/P: MCP6294T-E/SL: Extended Temperature, 14 lead PDIP package. Tape and Reel, Extended Temperature, 14 lead SOIC package. Extended Temperature, 14 lead SOIC package. Extended Temperature, 14 lead TSSOP package. MCP6293-E/SN: MCP6292-E/SN: MCP6291-E/SN: Temperature Range Device: MCP6291: MCP6291T: MCP6291RT: MCP6292: MCP6292T: MCP6293: MCP6293T: MCP6294: MCP6294T: MCP6295: MCP6295T: Single Op Amp Single Op Amp (Tape and Reel) (SOIC, MSOP, SOT-23-5) Single Op Amp (Tape and Reel) (SOT-23-5) Dual Op Amp Dual Op Amp (Tape and Reel) (SOIC, MSOP) Single Op Amp with Chip Select Single Op Amp with Chip Select (Tape and Reel) (SOIC, MSOP, SOT-23-6) Quad Op Amp Quad Op Amp (Tape and Reel) (SOIC, TSSOP) Dual Op Amp with Chip Select Dual Op Amp with Chip Select (Tape and Reel) (SOIC, MSOP) d) e) a) b) c) d) a) b) Temperature Range: E = -40 C to +125 C c) d) Package: OT = Plastic Small Outline Transistor (SOT-23), 5-lead (MCP6291, MCP6291R) CH = Plastic Small Outline Transistor (SOT-23), 6-lead (MCP6293) MS = Plastic MSOP, 8-lead P = Plastic DIP (300 mil body), 8-lead, 14-lead SN = Plastic SOIC, (3.90 mm body), 8-lead SL = Plastic SOIC (3.90 mm body), 14-lead ST = Plastic TSSOP (4.4 mm body), 14-lead a) b) c) d) a) b) c) d) MCP6294-E/SL: MCP6294-E/ST: MCP6295-E/SN: Extended Temperature, 8 lead SOIC package. MCP6295-E/MS: Extended Temperature, 8 lead MSOP package. MCP6295-E/P: Extended Temperature, 8 lead PDIP package. MCP6295T-E/SN: Tape and Reel, Extended Temperature, 8 lead SOIC package. (c) 2007 Microchip Technology Inc. DS21812E-page 33 MCP6291/1R/2/3/4/5 NOTES: DS21812E-page 34 (c) 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2007 Microchip Technology Inc. DS21812E-page 35 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 10/05/07 DS21812E-page 36 (c) 2007 Microchip Technology Inc. |
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